The present invention relates generally to semiconductor packaging and, more particularly, to a multi-chip (or multi-die) package incorporating a redistribution layer (RDL) interposer.
As known in the art, there are a variety of chip package techniques such as ball grid array (BGA), wire bonding, flip-chip, etc. for mounting a die on a substrate via the bonding points on both the die and the substrate. To ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are required to be of small in size, multi-pin connection, high speed, and high functionality.
Wire-bonding System-in-Package (WBSiP) technology is widely used because it can increase the capacity of the semiconductor package. WBSiP includes a plurality of chips, which are stacked and may be connected to each other by way of wire bonding. However, the conventional WBSiP encounters several problems, for example, the thickness of the package, ability to support fine pitch pad, and low-resistance/inductance IP.
Increased input-output (I/O) pin count combined with increased demands for high performance ICs has led to the development of flip-chip packages. Flip-chip technique uses bumps on bonding pads on chip to interconnect directly to the package medium. The chip is bonded face down to the package medium through the shortest path. The technique can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package.
However, the conventional flip-chip technique is facing the challenge of bump pitch limitation on the substrate. Besides, a high-performance FCBGA package is costly due to the expensive chip carrier substrate that typically comprises 1+2+1 or more-layer build up. The bottleneck of the flip-chip roadmap is the bump pitch of the substrate since the development and shrinkage of the bump pitch is much slower than the die shrinking and the increase of the pin count. Even the die shrinking will exceed the shrinkage of bump pitch resolution on substrate carrier in the future.
To conquer the issue of such technology gap, silicon interposer and TSV (Through Silicon Via) technology, and fine pitch bump technology are preferred solutions. However, the above-mentioned TSV-based technologies are expensive and involve complex fabrication processes.